The following is sample output from the show protocols command. The show protocols command shows the global and interface-specific status of any configured Level 3 protocol. This command was integrated into Cisco IOS XE Release 2.1. This command was integrated into Cisco IOS Release 12.2(33)SRA. The command was integrated in a release earlier than Cisco IOS Release 12.0(3)T. Virtual-Template-Virtual template interface.Virtual-Access-Virtual access interface.Ethernet-Institute of Electrical Electronics Engineers (IEEE) 802.3. # we have no idea what clock the target is running at.To display the configured protocols, use the show protocols command in user EXEC or privileged EXEC mode. # boot rom could have been playing with the PLL, so # Run with *real slow* clock by default since the # boot loader which verifies the flash exception table's checksum). # LPC1756 has 256kB of flash memory, managed by ROM code (including a #reset_config trst_and_srst srst_pulls_trst $_TARGETNAME configure -work-area-backup 0 $_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size 0x8000 Target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME Jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID # Adapt based on what transport is active. # LPC17xx chips support both JTAG and SWD transports. First, my cfg files, starting with my target device cfg file: # NXP LPC1756 Cortex-M3 with 256kB Flash and 32kB SRAM However, when I try to debug I run into issues. At the moment I have verification issues and need to sort that out but at this stage, it appears my JTAG setup is working and I am successfully communicating with the '1756. After programming I have the script perform a dump_image and the dumped image looks to be roughly correct. I believe I have the flash-upload side of things settled now. Eclipse Helios using Codesourcery ARM toolchain along with OpenOCD for debugging.
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